Flash memories, for example NAND flash devices, have become a key enabling technology for consumer applications and mobile storage applications such as flash cards, digital audio & video players, cell phones, USB flash drivers and solid state disks for HDD replacement. The density requirement is increasing and for example, NAND flash provides high density with low cost. For this reason, a great deal of attention has been paid to multilevel flash memories. In multilevel memory, rather than selecting between two levels to store a two state information element (a bit) in each cell, additional levels are employed to allow selecting between information elements having more than two states for each cell. For example, four levels can be used to represent a four state information element, and a four state information element can contain two bits. The memory cell density can be doubled without a die size increase if the four levels of data can be stored in one memory cell instead of two.
A two-level flash memory cell stores one of two logic states: data ‘1’ and data ‘0’, and the contents of each memory cell correspond to one bit. The conventional two-level flash memory cell can have one of two threshold voltages corresponding to data ‘1’ and data ‘0’. The threshold voltage distribution of a single level cell (SLC) in a NAND flash is shown in FIG. 1. Shown is a distribution 50 for a first cell state, and a distribution 52 for a second cell state. In this example, the cell states are assigned to data ‘1’ and data ‘0’, respectively (or vice versa). The ‘1’ state denotes that the cell turns on and can flow current. On the other hand, the ‘0’ indicates that the cell turns off and can not flow current. With only two states and one bit of data stored, SLC NAND Flash's Control Logic is able to conserve energy when managing the electrical charge during operations.
A four level flash memory cell stores one of four logic states, and the contents of each memory cell correspond to two bits. The four level flash memory cell can have one of four threshold voltages corresponded to data ‘11’, data ‘10’, data ‘00’ and data ‘01’. The threshold voltage distribution of a four-level MLC in a NAND flash is shown in FIG. 2. Shown are distributions 60,62,64,66 for four cell states. In this example, the cell states are assigned to data ‘11’, data ‘10’, data ‘00’ and data ‘01’ respectively. This employs the row direction assignment of two bits proposed by Ken Takeuchi, as described in U.S. Pat. No. 6,885,583 hereby incorporated by reference in its entirety. The two bits represent an upper page bit and a lower page bit. Thus: the cell assigned to data ‘11’ has Upper page=1 and Lower page=1;
the cell assigned to data ‘10’ has Upper page=1 and Lower page=0;
the cell assigned to data ‘00’ has Upper page=0 and Lower page=0; and
the cell assigned to data ‘01’ has Upper page=0 and Lower page=1.